Memory addressing in traditional processors is typically computed by adding two operands such as a base address and an offset address in order to arrive at an effective address. Base+offset addressing is typically used to address memory within data caches as well as data or instructions within other CPU memory units. For example, Table-Lookaside-Buffers (TLBs) typically use base+offset addition in order to access a buffer location within the TLB. Because an addition is typically performed to arrive at the effective address, traditional processors usually take at least two cycles to access the memory. A first cycle is used to add the base and offset addresses and a second cycle is used to access the memory. Consequently, because two cycles are usually needed to access the memory in a traditional processor, the cycle immediately following a load instruction cannot use the result of the load operation. This delay is referred to as “load latency.” Load latency is a performance limitation factor in traditional processors. Load latency often manifests itself in a pipelined processor as a load-use penalty with the load results being unavailable for two machine cycles.
Therefore, what is needed is a system and method that improves access to a memory array based on multiple operand addressing.